The bit transmission layer or physical layer (PHY) is the bottom layer in the O[pen]S[ystems]I[nterconnection] layer model, also called OSI reference model and denotes a layer model of the International Standards Organisation (ISO) which in turn serves as a design basis for communication protocols in computer networks.
The physical layer (PHY) is responsible for Combining, F[orward]E[rror]C[orrection], modulation, power control, spreading (C[ode]D[ivision]M[ultiple]A[ccess]) and the like PHY makes logical channels (transport channels for U[niversal]M[obile]T[elecommunications]S[ystem]) available to the security layer (D[ata]L[ink]L[ayer]) above it, in particular to a partial layer called M[edia]A[ccess]C[ontrol] Layer.
In principle D-PHY provides a flexible, low-cost and quick serial interface for communication links between components within a mobile device.
As illustrated in FIG. 3A, in modern mobile phones a data source, for example an application processor, provides image data as D-PHY signals to the M[obile]I[ndustry]P[rocessor]I[nterface]-D[isplay]S[erial]I[nterface] for display on a connected data sink, for example on a connected display. Also, a data sink such as an application processor, can receive, via a MIPI-C[amera]S[erial]I[nterface], image data in D-PHY format from a connected data source, such as from a connected camera.
A DSI or DSI-2 or CSI or CSI-2 or CSI-3 based on the D-PHY protocol comprises up to four differential data lines and a differential clock line, which electrically connect the application processor by means of a copper cable with the display and/or with the camera. The data rate per differential data line is up to 1.5 Gbps (Gigabit per second).
This conventional sending and receiving of the D-PHY-DSI signals or the D-PHY-CSI signals via one to four differential data signals and a differential clock line is illustrated by way of example in the D-PHY interface configuration of FIG. 3B by way of two data channels (=so called data lanes CH0+, CH0− and CH1+, CH1−) and a clock line (=so called clock lane CLK+, CLK−) between the modules of the master side (=data source, for example camera and/or application processor) and the modules of the slave side (=data sink, for example application processor and/or display unit).
In this context, as can be seen in FIG. 3A, up to ten copper lines are required for data transmission for each connected display or for each connected camera (for example four times two data lines and one time two clock lines).
As the resolution of displays and cameras increases the data rates from the application processor to the display/the camera also increase. The high-frequency electrical fields created during data transmission interfere with the sensitive adjacent receivers of high-frequency useful signals, such as, for example, with Bluetooth, G[lobal]P[ositioning]S[ystem], U[niversal]M[obile]T[elecommunications]S[ystem] or Wi-Fi-receivers and thus considerably impair their function.
Comprehensive and thus costly screening measures are required in order to ensure interference-free operation of the above mentioned receivers.
As the number of displays and cameras in modern mobile phones or comparable devices increases the sizes of cable harnesses in such devices can easily rise to up to sixty lines, just for the transmission of image data. Disadvantageously these cable harness sizes prevent further miniaturisation of such devices.